In certain applications, it is desirable to control the highest level and the lowest level of an input signal. This is referred to as high-side and low-side clamping. High-side clamping may be used to limit the input signal to a device to avoid damage. Such a device may be an analog-to-digital converter (ADC). If the input signal is a differential signal, low-side clamping may be used to create a symmetrical differential input signal around a common mode voltage when the high-side is clamped. The clamping also limits the maximum range input signal to the ADC. Low-side clamping may also be used to set a minimum voltage into a downstream device to ensure proper operation of the downstream device.
FIG. 1 illustrates a buffer 10 (a driver) receiving an analog differential input signal (IN+ and IN−), assumed to be sine waves. The buffer 10 generates analog differential output signals AIN+ and AIN− that are clamped for receiving by a particular ADC 12. The user selects the particular ADC 12 and may select the clamping requirements for the ADC 12 by providing certain control signals to the ClHi (clamp high-side) input terminal and Vcm (common mode voltage) input terminal of the buffer 10. In one embodiment, the buffer 10 may automatically adjust the low-side clamp voltage, since the high-side clamp and low-side clamp voltages are assumed to be symmetrical around the common mode voltage. The dashed lines above and below the sine waves signify the high-side and low-side clamp voltages. Any input signal above or below the clamp voltages is clamped to the respective clamp voltage.
FIG. 2 illustrates a conventional low-side clamp circuit 16 coupled to an emitter follower output stage 17 of a buffer, such as buffer 10. An input signal Vin at terminal 18 is coupled to the base of the NPN transistor QN1. Current flows through resistor R1, transistor QN1, and transistor QN2 between the supply voltage Vcc and ground. A high gain differential amplifier 20 has an inverting input coupled to a reference voltage Vref and a non-inverting input coupled to the resistor R1. The output of the differential amplifier 20 is coupled to the base of transistor QN2. The differential amplifier 20 uses feedback to control the current through transistor QN2 and resistor R1 such that the voltage at the resistor R1 equals the reference voltage Vref. The amplifier 20 maintains a constant collector current for transistor QN1.
The output voltage Vout is clamped to a desired low-side clamp voltage (ClLo) when Vin-Vbe tries to go below the clamp voltage. The user or the buffer sets ClLo by coupling the value ClLo+Vbe to the base of transistor Q2C. ClLo+Vbe is generated by a conventional voltage source. The transistor Q2C is connected in parallel with transistor QN1 by sharing its emitter and collector regions. The transistors are scaled to have the same current density when on. Therefore, they may have different areas to cause them to conduct different currents with the same Vbe. The transistor Q2C turns on when the voltage at its emitter reaches ClLo and supplies current to the load connected to the output terminal 22. Thus, the output voltage Vout cannot go below ClLo, and Vout is the maximum of ClLo or Vin-Vbe. The output impedance of transistor Q2C limits the accuracy of the clamp voltage.
One problem with the clamp circuit 16 is that is does not have a sharp response as Vin-Vbe approaches the clamp voltage, due to the clamp transistor Q2C not having a precise turn-on voltage. A sharp and accurate response is desired for an accurate low-side clamp voltage, especially when used in a buffer for a precision ADC.
Another problem with such “voltage mode” clamp circuits is that the clamp voltage, if too low, may cause a current source in the circuit that generates the value ClLo+Vbe to saturate. This creates a voltage offset in the clamp circuit.
Another problem with conventional low-side clamp circuits is that a varying offset between the intended clamp voltage and the actual clamp voltage may occur with varying load currents when the output is clamped.
What is needed is an accurate low-side clamp circuit with a sharp response to an input voltage falling below the clamp voltage and which can generate a very low clamp voltage.